Dynamicity Analysis of Delta MINs for MPSOC Architectures

Multistage interconnection network has been very frequently proposed as connection means in classical on-board multiprocessor systems, it promises to be the solution for the interconnection problems. This paper tries to adapt such networks for embedded system design. Our approach is to analyze the dynamicity of the link permutation of Delta MINs for MPSOC architectures. This paper presents the design methodology and the performance evaluation of delta MINs. SystemC timed simulations of the proposed MIN gives interesting results. These later should results derived from timing simulation are given. This study is to be used in future work in order to evaluate the NOC reconfigurability in which the connections change dynamically at run time.